PGAS and APGAS
Global address-space abstractions for parallel programs, including UPC and UPC++, data locality, remote-memory operations and asynchronous communication.
My research focuses on the Partitioned Global Address Space (PGAS) programming model and its practical trade-offs: programmability, communication overhead, performance, scalability and energy efficiency.
The work combines implementations of scientific kernels, performance measurements and models that help explain how data movement and hardware characteristics affect parallel applications.
Global address-space abstractions for parallel programs, including UPC and UPC++, data locality, remote-memory operations and asynchronous communication.
Analysis of computation and communication costs, memory traffic, cache behavior, irregular access patterns and performance models.
Comparative evaluation of UPC, MPI and OpenMP on multicore and multi-node systems, including energy measurements and scaling across many cores.
Scientific kernels including sparse matrix-vector multiplication and a two-dimensional heat equation, with applications to diffusion and irregular meshes.
The entries below are based on the supplied papers and doctoral thesis. The publication year is shown as published or identified in the source material.
Jérémie Lagravière, Johannes Langguth, Martina Prugger, Phuong Hoai Ha and Xing Cai. arXiv:2102.03614.
Compares UPC and UPC++ in terms of programming style, programmability, performance predictability and execution performance, using a 2D heat equation and sparse matrix-vector multiplication across single-node, multi-node and many-core platforms.
PhD thesis, Department of Informatics, Faculty of Mathematics and Natural Sciences, University of Oslo; research conducted with Simula Research Laboratory.
Brings together work on PGAS programming, UPC/UPC++, performance and energy efficiency, fine-grained irregular communication, and mesh-based scientific computation.
Jérémie Lagravière, Johannes Langguth, Martina Prugger, Lukas Einkemmer, Phuong Hoai Ha and Xing Cai. Scientific Programming, 2019, Article ID 6825728.
Studies transformations such as thread privatization, block-wise transfers, and message condensation/consolidation to reduce the cost of fine-grained irregular communication; develops performance models based on data movement and hardware parameters.
Jérémie Lagravière, Johannes Langguth, Mohammed Sourouri, Phuong H. Ha and Xing Cai. International Conference on High Performance Computing & Simulation (HPCS), 2016.
Evaluates UPC against MPI and OpenMP using NAS Parallel Benchmark kernels, on a single 16-core node and a multi-node system scaling to 1024 physical cores, including energy-efficiency analysis.
Sudeep Kanur Chandra Shekar, Georgios Georgakarakos, Antti Siirilä and Jérémie Lagravière, with additional co-authors as listed in the proceedings. HPCS 2013.
Implements a reduced minimum-sum LDPC decoding algorithm on the HeMPS multiprocessor system-on-chip framework and studies throughput and speed-up using a network-on-chip architecture.